1. Field of the Invention
The present invention relates to memory expansion devices. More particularly, memory expansion apparatus requiring a minimum of logic circuitry and responding to execution of a particular function code is contemplated.
2. Brief Description of the Prior Art
Typical prior art devices for memory expansion are found in Gnadeberg et al U.S. Pat. No. 3,984,818, Taddei Pat. No. 3,972,025 and Elward U.S. Pat. No. 3,970,999. The prior art devices require the repeated decoding of the paging address scheme, as in Elward, for example, and require use of substantial and complicated logic circuitry.